oopsie dumb file
[teletype.git] / tele-pi / tele-pi.pro
1 update=Sun 12 Sep 2021 12:12:16 AM EDT
2 version=1
3 last_client=kicad
4 [general]
5 version=1
6 RootSch=
7 BoardNm=
8 [cvpcb]
9 version=1
10 NetIExt=net
11 [eeschema]
12 version=1
13 LibDir=
14 [eeschema/libraries]
15 [pcbnew]
16 version=1
17 PageLayoutDescrFile=
18 LastNetListRead=
19 CopperLayerCount=2
20 BoardThickness=1.6
21 AllowMicroVias=0
22 AllowBlindVias=0
23 RequireCourtyardDefinitions=0
24 ProhibitOverlappingCourtyards=1
25 MinTrackWidth=0.2
26 MinViaDiameter=0.4
27 MinViaDrill=0.3
28 MinMicroViaDiameter=0.2
29 MinMicroViaDrill=0.09999999999999999
30 MinHoleToHole=0.25
31 TrackWidth1=0.25
32 TrackWidth2=0.5
33 TrackWidth3=1
34 TrackWidth4=2
35 ViaDiameter1=0.8
36 ViaDrill1=0.4
37 dPairWidth1=0.2
38 dPairGap1=0.25
39 dPairViaGap1=0.25
40 SilkLineWidth=0.12
41 SilkTextSizeV=1
42 SilkTextSizeH=1
43 SilkTextSizeThickness=0.15
44 SilkTextItalic=0
45 SilkTextUpright=1
46 CopperLineWidth=0.2
47 CopperTextSizeV=1.5
48 CopperTextSizeH=1.5
49 CopperTextThickness=0.3
50 CopperTextItalic=0
51 CopperTextUpright=1
52 EdgeCutLineWidth=0.05
53 CourtyardLineWidth=0.05
54 OthersLineWidth=0.15
55 OthersTextSizeV=1
56 OthersTextSizeH=1
57 OthersTextSizeThickness=0.15
58 OthersTextItalic=0
59 OthersTextUpright=1
60 SolderMaskClearance=0
61 SolderMaskMinWidth=0
62 SolderPasteClearance=0
63 SolderPasteRatio=-0
64 [pcbnew/Layer.F.Cu]
65 Name=F.Cu
66 Type=0
67 Enabled=1
68 [pcbnew/Layer.In1.Cu]
69 Name=In1.Cu
70 Type=0
71 Enabled=0
72 [pcbnew/Layer.In2.Cu]
73 Name=In2.Cu
74 Type=0
75 Enabled=0
76 [pcbnew/Layer.In3.Cu]
77 Name=In3.Cu
78 Type=0
79 Enabled=0
80 [pcbnew/Layer.In4.Cu]
81 Name=In4.Cu
82 Type=0
83 Enabled=0
84 [pcbnew/Layer.In5.Cu]
85 Name=In5.Cu
86 Type=0
87 Enabled=0
88 [pcbnew/Layer.In6.Cu]
89 Name=In6.Cu
90 Type=0
91 Enabled=0
92 [pcbnew/Layer.In7.Cu]
93 Name=In7.Cu
94 Type=0
95 Enabled=0
96 [pcbnew/Layer.In8.Cu]
97 Name=In8.Cu
98 Type=0
99 Enabled=0
100 [pcbnew/Layer.In9.Cu]
101 Name=In9.Cu
102 Type=0
103 Enabled=0
104 [pcbnew/Layer.In10.Cu]
105 Name=In10.Cu
106 Type=0
107 Enabled=0
108 [pcbnew/Layer.In11.Cu]
109 Name=In11.Cu
110 Type=0
111 Enabled=0
112 [pcbnew/Layer.In12.Cu]
113 Name=In12.Cu
114 Type=0
115 Enabled=0
116 [pcbnew/Layer.In13.Cu]
117 Name=In13.Cu
118 Type=0
119 Enabled=0
120 [pcbnew/Layer.In14.Cu]
121 Name=In14.Cu
122 Type=0
123 Enabled=0
124 [pcbnew/Layer.In15.Cu]
125 Name=In15.Cu
126 Type=0
127 Enabled=0
128 [pcbnew/Layer.In16.Cu]
129 Name=In16.Cu
130 Type=0
131 Enabled=0
132 [pcbnew/Layer.In17.Cu]
133 Name=In17.Cu
134 Type=0
135 Enabled=0
136 [pcbnew/Layer.In18.Cu]
137 Name=In18.Cu
138 Type=0
139 Enabled=0
140 [pcbnew/Layer.In19.Cu]
141 Name=In19.Cu
142 Type=0
143 Enabled=0
144 [pcbnew/Layer.In20.Cu]
145 Name=In20.Cu
146 Type=0
147 Enabled=0
148 [pcbnew/Layer.In21.Cu]
149 Name=In21.Cu
150 Type=0
151 Enabled=0
152 [pcbnew/Layer.In22.Cu]
153 Name=In22.Cu
154 Type=0
155 Enabled=0
156 [pcbnew/Layer.In23.Cu]
157 Name=In23.Cu
158 Type=0
159 Enabled=0
160 [pcbnew/Layer.In24.Cu]
161 Name=In24.Cu
162 Type=0
163 Enabled=0
164 [pcbnew/Layer.In25.Cu]
165 Name=In25.Cu
166 Type=0
167 Enabled=0
168 [pcbnew/Layer.In26.Cu]
169 Name=In26.Cu
170 Type=0
171 Enabled=0
172 [pcbnew/Layer.In27.Cu]
173 Name=In27.Cu
174 Type=0
175 Enabled=0
176 [pcbnew/Layer.In28.Cu]
177 Name=In28.Cu
178 Type=0
179 Enabled=0
180 [pcbnew/Layer.In29.Cu]
181 Name=In29.Cu
182 Type=0
183 Enabled=0
184 [pcbnew/Layer.In30.Cu]
185 Name=In30.Cu
186 Type=0
187 Enabled=0
188 [pcbnew/Layer.B.Cu]
189 Name=B.Cu
190 Type=0
191 Enabled=1
192 [pcbnew/Layer.B.Adhes]
193 Enabled=1
194 [pcbnew/Layer.F.Adhes]
195 Enabled=1
196 [pcbnew/Layer.B.Paste]
197 Enabled=1
198 [pcbnew/Layer.F.Paste]
199 Enabled=1
200 [pcbnew/Layer.B.SilkS]
201 Enabled=1
202 [pcbnew/Layer.F.SilkS]
203 Enabled=1
204 [pcbnew/Layer.B.Mask]
205 Enabled=1
206 [pcbnew/Layer.F.Mask]
207 Enabled=1
208 [pcbnew/Layer.Dwgs.User]
209 Enabled=1
210 [pcbnew/Layer.Cmts.User]
211 Enabled=1
212 [pcbnew/Layer.Eco1.User]
213 Enabled=1
214 [pcbnew/Layer.Eco2.User]
215 Enabled=1
216 [pcbnew/Layer.Edge.Cuts]
217 Enabled=1
218 [pcbnew/Layer.Margin]
219 Enabled=1
220 [pcbnew/Layer.B.CrtYd]
221 Enabled=1
222 [pcbnew/Layer.F.CrtYd]
223 Enabled=1
224 [pcbnew/Layer.B.Fab]
225 Enabled=1
226 [pcbnew/Layer.F.Fab]
227 Enabled=1
228 [pcbnew/Layer.Rescue]
229 Enabled=0
230 [pcbnew/Netclasses]
231 [pcbnew/Netclasses/Default]
232 Name=Default
233 Clearance=0.2
234 TrackWidth=0.25
235 ViaDiameter=0.8
236 ViaDrill=0.4
237 uViaDiameter=0.3
238 uViaDrill=0.1
239 dPairWidth=0.2
240 dPairGap=0.25
241 dPairViaGap=0.25
242 [schematic_editor]
243 version=1
244 PageLayoutDescrFile=
245 PlotDirectoryName=
246 SubpartIdSeparator=0
247 SubpartFirstId=65
248 NetFmtName=
249 SpiceAjustPassiveValues=0
250 LabSize=50
251 ERC_TestSimilarLabels=1